Dubois M. Parallel computer organization and design / M.Dubois, M.Annavaram, P.Stenstrom. - Cambridge; New York: Cambridge univ. press, 2012. - xvii, 542 p.: ill. - Пер. загл.: Организация и проектирование параллельных компьютеров. - ISBN 978-0-521-88675-8  Место хранения:   02 | Отделение ГПНТБ СО РАН | Новосибирск

Оглавление / Contents

Preface ........................................................ xi 1 Introduction ................................................. l 1.1 What is computer architecture? .......................... 2 1.2 Components of a parallel architecture ................... 5 1.3 Parallelism in architectures ........................... 13 1.4 Performance ............................................ 17 1.5 Technological challenges ............................... 26 Exercises ................................................... 30 2 Impact of technology ........................................ 36 2.1 Chapter overview ....................................... 36 2.2 Basic laws of electricity .............................. 37 2.3 The MOSFET transistor and CMOS inverter ................ 39 2.4 Technology scaling ..................................... 43 2.5 Power and energy ....................................... 45 2.6 Reliability ............................................ 54 Exercises ................................................... 71 3 Processor microarchitecture ................................. 74 3.1 Chapter overview ....................................... 74 3.2 Instruction set architecture ........................... 75 3.3 Statically scheduled pipelines ......................... 91 3.4 Dynamically scheduled pipelines ....................... 111 3.5 VLIW microarchitectures ............................... 140 3.6 EPIC microarchitectures ............................... 157 3.7 Vector microarchitectures ............................. 158 Exercises .................................................. 165 4 Memory hierarchies ......................................... 193 4.1 Chapter overview ...................................... 193 4.2 The pyramid of memory levels .......................... 194 4.3 Cache hierarchy ....................................... 198 4.4 Virtual memory ........................................ 212 Exercises .................................................. 224 5 Multiprocessor systems ..................................... 232 5.1 Chapter overview ...................................... 232 5.2 Parallel-programming model abstractions ............... 233 5.3 Message-passing multiprocessor systems ................ 239 5.4 Bus-based shared-memory systems ....................... 246 5.5 Scalable shared-memory systems ........................ 276 5.6 Cache-only shared-memory systems ...................... 293 Exercises .................................................. 298 6 Interconnection networks ................................... 309 6.1 Chapter overview ...................................... 309 6.2 Design space of interconnection networks .............. 311 6.3 Switching strategies .................................. 319 6.4 Topologies ............................................ 322 6.5 Routing techniques .................................... 330 6.6 Switch architecture ................................... 337 Exercises .................................................. 339 7 Coherence, synchronization, and memory consistency ......... 342 7.1 Chapter overview ...................................... 342 7.2 Background ............................................ 344 7.3 Coherence and store atomicity ......................... 350 7.4 Sequential consistency ................................ 375 7.5 Synchronization ....................................... 388 7.6 Relaxed memory-consistency models ..................... 398 7.7 Speculative violations of memory orders ............... 411 Exercises .................................................. 415 8 Chip multiprocessors ....................................... 425 8.1 Chapter overview ...................................... 425 8.2 Rationale behind CMPs ................................. 426 8.3 Core multi-threading .................................. 429 8.4 Chip multiprocessor architectures ..................... 446 8.5 Programming models .................................... 459 Exercises .................................................. 482 9 Quantitative evaluations ................................... 488 9.1 Chapter overview ...................................... 488 9.2 Taxonomy of simulators ................................ 490 9.3 Integrating simulators ................................ 498 9.4 Multiprocessor simulators ............................. 500 9.5 Power and thermal simulations ......................... 508 9.6 Workload sampling ..................................... 510 9.7 Workload characterization ............................. 514 Exercises .................................................. 516 Index ......................................................... 521